Crosstalk between adjacent clock signal generators can result in spurious emissions or spurs within a frequency band of interest. The frequency band of interest might be a measurement band within which noise must not exceed a certain level, for example.
In high frequency applications above 10 GHz for instance, a serializer/deserializer (serdes) Clock Multiplier Unit (CMU) with a fractional-N based frequency agile cleanup Phase Locked Loop (PLL) function must satisfy very tight noise specifications. However, the use of a fractional-N cleanup PLL to clean up an input reference signal to the CMU requires that the PLL must also be low bandwidth to filter out fractional-N noise or spurs and noise. This in turn can cause poor CMU crosstalk immunity, which can be especially problematic when multiple CMUs supply clock signals which are close in frequency. Integrating many CMUs on one die or board or within one package can cause CMU crosstalk to be a limiting factor for clock signal generation performance such as jitter performance.
Cleanup PLLs could be displaced from each other to reduce crosstalk. The cost associated with providing external cleanup PLLs, however, tends to be much greater than the cost of integrating PLLs on the same chip or board or in the same package as other components, such as the CMUs in the above example. Providing space between PLLs also consumes “real estate”, which is limited in a chip, in a package, or on a board. In some applications, dozens of PLLs are needed.
Wider bandwidth PLLs might also reduce crosstalk, but as noted above, narrow bandwidth is preferred for cleanup PLLs. The narrow bandwidth preference might be based on specification requirements for removing jitter on incoming signals, for instance.